| 摘要 |
<p>This disclosure describes a method to use a clock edge management system (800) in semiconductor devices for noise sensitive systems that includes digital circuits (828) and analog circuits (820). The system (800) includes the following: a high frequency clock source (802), an analog clock processing circuit (804) to produce an analog clock signal (814) used by analog circuits (820), a digital clock processing circuit (806) to produce a digital clock signal (822) used by digital circuits (828). The system (800) combines the outputs of a first comparator (808) and a second comparator (810) with a Boolean logic gate (812) to produce an analog clock window signal Wns. The system (800) then produces delay into the digital clock signal so that it is delayed beyond the noise sensitive region of the analog circuits.</p> |
