发明名称 DYNAMIC RAM
摘要 PURPOSE:To reduce the power consumption of a dynamic RAM by delaying the actuation of a sense amplifier in an automatic refresh mode. CONSTITUTION:In an automatic refresh mode, a refresh control signal phiVef' supplied through an OR gate G2 is set at L to close AND gates G1, G3 of an action timing generating circuit phipa-G for sense amplifier. A gate G1 is opened after the delay time of a delay circuit DL2, and a drive circuit phipa1DV5 is active. Then an action timing signal phipa1 for sense amplifier is delivered with a fixed time delayed from the start of the automatic-refresh mode. The amplifying action of the sense amplifier is carried out after the storage information of a RAM is taken out sufficiently to a data line. Then the through current or the reactive current produced by the discharge of the dat line of an H level is eliminated. Thus the power consumption of a dynamic RAM is reduced. The same effect is secured by controlling the generation of action timing signals with a control signal having a slow rise.
申请公布号 JPS60246096(A) 申请公布日期 1985.12.05
申请号 JP19840100489 申请日期 1984.05.21
申请人 HITACHI SEISAKUSHO KK 发明人 ITOU KAZUYA
分类号 G11C11/406;G11C11/34;G11C11/409;(IPC1-7):G11C11/34 主分类号 G11C11/406
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