发明名称 PHASE UNCERTAINTY ELIMINATING CIRCUIT
摘要 PURPOSE:To reduce the time required for eliminating phase uncertainty by detecting a repulling-in phase in a specific order at all times from a present phase state when a pulling-in phase is transited due to phase slip in a 4-phase PSK demodulator. CONSTITUTION:A signal selecting circuit 7 an output SC of an exclusive OR circuit 5, its inverting output, the 2nd output SB of a control signal generating circuit 1 and its inverting output with an output SD of an initial state detecting circuit 8 to output signals SE, SF. The 2nd output SF of the signal selection circuit 7 and the 1st data input P are inputted to an exclusive OR circuit 2 and the 1st output SE of the signal selection circuit 7 controls a signal replacing circuit 4. If a phase slit takes place, the phase of a reproduced carrier has the highest probability in transiting to an adjacent phase rotated by pi/2 and 3/2pi. Through the use of the characteristic, the time for repulling-in is reduced by detecting the repulling-in phase when the pulling-in phase is transited due to phase slip in the order of pi/2, 3/2pi and pi at all times.
申请公布号 JPS60246157(A) 申请公布日期 1985.12.05
申请号 JP19840102082 申请日期 1984.05.21
申请人 NIPPON DENKI KK 发明人 ASADA JIYUNICHI;OGASAWARA MASAYUKI;TAKEDA TOSHIYUKI
分类号 H04L27/22;H04L27/227 主分类号 H04L27/22
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