| 摘要 |
PURPOSE:To reduce the load on a common controller by designating a line signal transmission time interval from the common controller and allowing the hardware to stop the line signal after a designating time is elapsed. CONSTITUTION:The transmission time length is written in synchronizing with a channel number generating counter 4 to an address corresponding to the transmission channel number of a timing memory 7 by the said number and the transmission time to an address input selector 5 and a data input selector 6 in the common controller 9 at line signal transmission and the signal transmission request is registered in the memory 7. A line signal transmission control circuit 8 commands the signal transmission to a line signal transmitter 2 by using an output of the counter 4 as the channel number. The memory 7 outputs sequentially the signal transmission time length at each channel, reads it by using the control circuit 8 and when the value is 1 or over, 1 is subtracted and the selector 6 is used again to write it to the memory 7. When the read data is ''0'', the control circuit 8 commands the signal transmission stop at the channel represented by the counter 4 to the transmitter 2. |
