| 摘要 |
PURPOSE:To adjust simply the length of logical ''0'' and logical ''1'' by giving logical ''1'' to the 1st input terminal of the 1st NAND gate, giving logical ''0'' to an input terminal of an inverting gate and connecting respectively the 1st and 2nd input terminals of the 2nd NAND gate and two of plural delay output terminals. CONSTITUTION:Explanation is made as to the adjustment that the period of logical ''0'' of an output waveform from an oscillator 1 is shorter than the normal value as shown in Fig. (a). A tap 10 and the 3rd connecting terminal 22, and the 6th connecting terminal and the 1st and 4th connecting terminals 20, 23 are connected respectively. Then, for example, a tap 11 and the 2nd connecting terminal 21 are connected. A signal [Fig. (d)] where the period of logical ''0'' is made longer is obtained at an output terminal 26 by ORing an output signal of the tap 10 [Fig. (b)] and an output signal of the tap 11 [Fig (c)] by the 1st three- input NAND gate 3. The period of logical ''0'' is made sequentially longer by changing sequentially the connected tap as taps 11, 12...19. |
