| 摘要 |
PURPOSE:To attain stable decoding by providing each means and plural latch means for ternary discrimination, window signal generation, delay, serial/parallel conversion, discrimination of plural outputs and gating for plural outputs and unifying an input section for a ternary serial signal inputted in a different bit number where binary data is assigned at each bit to a front or a rear part of an index signal to simplify the circuit constitution. CONSTITUTION:The data decoder extracts a parallel binary data corresponding to a bit number from plural ternary serial signals in a different bit number transmitted through a signal line. For example, when a 5-bit tri-state serial signal of a ternary serial signal S23 is inputted, a binary data signal S24 and an index signal S25 are generated and a binary data 00101 is outputted from outputs D0-D4 of a serial parallel converting means 13. Moreover, a discriminating means 26 generates a 5-bit discrimination signal S35 and a gate means 27 generates a 5-bit gate output signal S36, the D0-D4 outputs are latched by a 5-bit latch means 15a at the leading edge of the 5-bit gate output signal S36 to obtain a stable binary data output 00101 at X0, X1, X2, X3 and X4. |
