| 摘要 |
PURPOSE:To attain the large read/write timing margin width in a short access cycle as well as a high degree of integration and a high speed for a RAM device, by uniforming the same signal transmission conditions during which an address signal is decoded into a selection signal. CONSTITUTION:Each word line selection signal is transmitted to a word line WL via a three-input NAND, a two-input NOR, a two-input MAND and an inverter. The same number of logical circuits is kept within a signal route until address signals A0-A7 are decoded to selection signals. At the same time, the logical circuits have the same circuit constitution at the same decoding stage. In this case, the variance of the transmission delay time of each signal route is unified and also reduced for a period during which the signals A0-A7 are decoded to selection signals X0-Xm even though each logical circuit has some transmission delay. Thus the relatively large read/write timing margin width is secured although the access cycle is reduced. This avoids the destruction of storage information due to the double selection. |
