| 摘要 |
PURPOSE:To prevent out-of-synchronism caused by a cycle slip of a PLL circuit, by controlling the width of a gate signal for detecting a synchronizing signal, by a value of an output of a counter for deciding the out-of-synchronism. CONSTITUTION:A reference value is set in advance to a decoder 14, and at the time point when a carry signal 8a of a counter 8 has counted up to this value, a selecting signal 14a becomes a logical value ''1'', and a gate signal 16a is switched to a gate signal 16b having large pulse width. Accordingly, when the quantity of a cycle slip of a PLL circuit 4 is within a bit clock of a specified value, a synchronizing signal can be detected again, and no out-of-synchronism is caused. Accordingly, it can be prevented that a jarring sound of a digital signal regenerating device is regenerated. |
