发明名称 TIMING EXTRACTING CIRCUIT
摘要 <p>PURPOSE:To quicken a rise time of a timing clock by enlarging the amplitude of an input of a band pass filter by an integration circuit and a variable gain amplifier. CONSTITUTION:A random digital signal is inputted to a rectifying circuit 10. In the rectifying circuit 10, this random signal is rectified, and inputted to an integration circuit 50 and a variable gain amplifier 60. When a rectifying wave is inputted to a transistor of the integration circuit 50, a collector current flows and charge is accumulated in a capacitor. A voltage of a frequency appearing in the upper end of a resistance by a time constant of a CR circuit is applied as an input voltage of a variable impedance element, and an output of the variable gain amplifier 60 rises most suddenly in the beginning, and thereafter, settles down gradually to a prescribed value. Therefore, the input amplitude of a band pass filter 20 becomes large, therefore, a rise time of a timing clock signal can be quickened.</p>
申请公布号 JPS60245330(A) 申请公布日期 1985.12.05
申请号 JP19840100387 申请日期 1984.05.21
申请人 FUJITSU KK 发明人 TAKADA AKIHIKO
分类号 H04L7/027 主分类号 H04L7/027
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