| 摘要 |
PURPOSE:To prevent the through-current flowing via an outout buffer by delaying the timing the OFF-ON timing of one of paired transistors having polarities adverse to each other compared with the ON-OFF timing of the other transistor. CONSTITUTION:When the signal supplied to a point E is changed to a low level from a high level, a transistor TR14 of a delay circuit is turned on with a TR16 turned off respectively. In this case, a TR12 is kept at a high level for the delay time td produced by the TR14. Therefore a TR15 is changed to ON from OFF after the time td from OFF of the TR16. Then the TR16 is changed to ON from OFF after the time td from OFF of the TR16. Then the TR16 is changed to ON from OFF after the time td from off of the TR15. In such a way, at least one of both TRs can be kept off by delaying the OFF-ON timing of one of paired TRs 15 and 16 compared with the ON-OFF timing of the other TR. |
