发明名称 |
Refresh circuit for dynamic memory of a data processor employing a direct memory access controller |
摘要 |
In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.
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申请公布号 |
US4556952(A) |
申请公布日期 |
1985.12.03 |
申请号 |
US19810292075 |
申请日期 |
1981.08.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BREWER, JAMES A.;EGGEBRECHT, LEWIS C.;KUMMER, DAVID A.;MCHUGH, PATRICIA P. |
分类号 |
G11C11/406;(IPC1-7):G06F13/00 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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