| 摘要 |
PURPOSE:To guarantee simply the contents of data by outputting an access inhibition signal during the access of a CPU for accessing data in each byte, and making a CPU for accessing data in each word wait to access. CONSTITUTION:When a CPU1 is to access dual port memories 3, 4 in each byte length, an access signal is transmitted from the CPU1 to the memories 3, 4 through memory access signal lines 14, 13 and the CPU1 can access the memories 3, 4 in each byte. During said access, a memory access signal from a CPU2 is inhibited by a memory access inhibition signal. In addition, a waiting signal is outputted to the CPU2 and the CPU2 is kept at waiting status without accessing the memories 3, 4. |
