| 摘要 |
A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders, to allow slower bits to skip past a stage while faster bits must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.
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