| 摘要 |
PURPOSE:To enable to reduce the junction leakage current by a method wherein an inversion preventing layer is formed on the stepped part of one side of the sidewalls of a groove through an element isolation material buried in the interior of the groove. CONSTITUTION:An etching is performed on the main surface of a substrate 21 to the exfent of 0.3mum using a CVD oxide film 22 as a mask, whereby a stepping is formed on only one side of the mutually opposing sidewalls of a groove 27 in the substrate 21. Then, a CVD oxide film 30 is buried in the interior of the groove 27 and P<-> type field inversion preventing layers 31 are formed. As the P<-> type inversion preventing layer 31 is being formed on one side (the side of the N channel MOS transistor) of the mutually opposing sidewalls of the groove 27 through the CVD oxide film (element isolation material) 30 buried in the interior of the groove 27 in such a way, that is, in the vicinit of the junction point of the N<+> type source and drain regions 34 and 35 and the P type silicon substrate 21, the junction leakage current between both regions holding the groove between them can be reduced and the element characteristics can be improved. |
