| 摘要 |
An analog speed error signal, developed by comparing actual and desired speeds, is processed into a control voltage through a two condition circuit network. When the error signal is more than a predetermined percentage of the desired speed, the network has a unity gain and the control voltage equals the error signal. When the error signal becomes less than the predetermined percentage, the network is shifted into a hybrid form by inserting an integrator loop into the gain circuit so that the control voltage and error signal are not directly proportional. The control voltage is converted into a series of proportional width pulses which are applied to vary the generator output to control locomotive speed. The pulse width varies in part from the error signal variation but also in part from an acceleration signal to anticipate the achievement of desired speed. When the hybrid network is in use, the pulse width speed control feeds back to drive the error signal to zero. The control voltage and acceleration signal are also applied to a clock and reversible counter network which controls the locomotive throttle position. The counter steps up or down, to increase or decrease the throttle, at a clock frequency established by the absolute value of the control voltage whose polarity further designates the requirement for speed increase or decrease. A high level of acceleration, however, overrides to reverse the count direction to prevent overshooting the desired speed. A moderate acceleration level inhibits further counting and speed is then varied only by the pulse width modulation network. |
