| 摘要 |
PURPOSE:To eliminate the need to provide an exclusive area for a ROM in a gate array by constituting the ROM by using transistors (Tr) arrayed laterally in a column in the gate array as information storage and address selection TRs in the same column. CONSTITUTION:Storage blocks 21a-21d, a MOSTr6e, and a logical inversion type buffer 9 are coupled laterally to constitute a ROM main body 22. For example, if a source voltage value appears at a row decoding output 4a and a column decoding output 14 as the result of the decoding of address inputs 2 and 3, and 11 and 12, logic 1 is outputted to an information output terminal 10. Then, when the source voltage value is outputted to a row decoding output 4b and a column output 14a, the potential of a bit line 5f does not varies and logic 0 appears at a terminal 10 because the drain or source of a MOSTr15j is not connected to the source or drain of a MOSTr20a. Thus, the ROM is constituted to eliminate the need to provide the exclusive area for the ROM in the gate array and also forms the ROM efficiently in the gate array. |
