发明名称 INTEGRATED LOGIC CIRCUIT
摘要 PURPOSE:To eliminate the need for a resistor connected externally by holding the state of a two-way terminal and keeping the state of a bus line just before when outputs connected to a bus line go all to high impedance so as to prevent the bus line from going to an uncertain level. CONSTITUTION:An output of the 1st, 2nd tri-state circuits 1, 2 is connected respectively by a signal line 12 and to an input of an input circuit 3. When the level of a control signal 10 is logical ''1'', the 1st tri-state output circuit 1 outputs its data input signal 13 and an output of the 2nd tri-state output circuit 2 goes to high impedance state in this circuit. When the control signal 10 is logical ''0'', an output of the 1st tri-state output circuit 1 goes to high impedance state, and the state of the two-way terminal 5 of an integrated circuit just state is held via the input circuit 3 and the 2nd tri-state output circuit 2. Thus, the input state of the input circuit 3 is logical ''1'' or ''0'' at all times and does not go to the uncertain state.
申请公布号 JPS60242724(A) 申请公布日期 1985.12.02
申请号 JP19840099109 申请日期 1984.05.17
申请人 NIPPON DENKI KK 发明人 OOUCHI YASUNORI
分类号 H03K19/0175;G06F13/40;(IPC1-7):H03K19/00 主分类号 H03K19/0175
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