发明名称 CONTROL METHOD OF ARRAY PROCESSOR
摘要 PURPOSE:To enable an array processor to execute matrix multiplication processing which is self-completed by setting a 1-bit flag and a 2-bit flag to the input data and a processing element respectively. CONSTITUTION:A vector bj is transferred to the adjacent processing elements PE every processing unit time point. Thus all elements PE perform the inner product arithmetic and store the results of these arithmetics at a time point 5. A PE1 decides that the end flag added to a supplied vector b6 is equal to 1 before the arithmetic processing is started at a time point 6. Then the PE sets an output flag at 1 and transmits its own processing state to the PE2, 3 and 4 successively. The vector bj is transferred to the adjacent PE at a time point 7. Then a PE2 performs the processing and control actions like the PE1 at a time point 6. When the processing is over at a time point 9, the result of multiplication is obtained with matrices A and B respectively.
申请公布号 JPS60241155(A) 申请公布日期 1985.11.30
申请号 JP19840096656 申请日期 1984.05.16
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 TAKAHASHI JIYUNICHI;HATSUTORI SANSHIROU;KIMURA TAKASHI;IWATA ATSUSHI
分类号 G06F15/80;G06F15/16;G06F15/177 主分类号 G06F15/80
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