发明名称 MEMORY
摘要 PURPOSE:To read and write the desired data with a single access for the data set within the width of a data bus by using a tag line for each minimum address enable data. CONSTITUTION:When it is desired in a processing mode to read out data of bytes D6-D9, ''1'', ''1'', ''0'' and ''0'' are supplied to tag lines 8-11 respectively. Here incrementers 13 and 14 output the address signal obtained by adding +1 to an address A1 respectively. The data of a byte D8 is read out to a data bus 4 from a memory bank 17; while the data of the byte D9 is read out of a memory bank 18 and sent to a data bus 5. Then the data of bytes D6 and D7 are read out of memory banks 19 and 20 according to the address A1 and sent to data buses 6 and 7 respectively. Thus it is possible to read out the data of four bytes of D6-D8.
申请公布号 JPS60241143(A) 申请公布日期 1985.11.30
申请号 JP19840098226 申请日期 1984.05.16
申请人 NIPPON DENKI KK 发明人 SATOU HIROSHI
分类号 G06F12/04;G06F12/02;G06F12/06 主分类号 G06F12/04
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