发明名称 DC CLAMPING CIRCUIT
摘要 PURPOSE:To prevent deterioration of picture quality by making time constant successively larger during the period of clamp pulse, making DC reproducing capacity large by small time constant, and absorbing lateral noise generated by small time constant by large time constant. CONSTITUTION:A picture signal v1 to be clamped is supplied from a terminal 7, and pulses P1, P2 are supplied to terminals 14, 15 respectively, and reference potential E0 is impressed to a terminal 16. Switching SW circuits 12, 13 are made on by pulses P1, P2, and on resistance of the circuit 12 is made smaller than on resistance of the circuit 13. When the pulse P1 is inputted, the circuit 12 is made on, and large DC reproducing capacity is obtained by time constant of small on resistance. Potential E0 is impressed to a capacitor C9 and the signal v1 inputted through a low output impedance circuit 8 is clamped rapidly to potential E0. Pulse P2 is impressed at the time of ending of pulse P1, and the circuit 13 is made on. Potential E0 is impressed in large time constant of high on resistance, and video signals are clamped without following noise, and video signals v2 are outputted through a high input impedance circuit 10.
申请公布号 JPS60241374(A) 申请公布日期 1985.11.30
申请号 JP19840096415 申请日期 1984.05.16
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU MASANORI
分类号 H04N5/18 主分类号 H04N5/18
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