| 摘要 |
PURPOSE:To generate a false fault at the execution of an instruction in an optinal instruction address by providing the titled device with a false fault address register, a false fault address setting means, a coincidence circuit, and a false fault generating means. CONSTITUTION:An instruction address is set up in the false fault address register 11 from any one of an address setting path 101 obtained from a soft instruction, a setting path 102 from a service processor and a setting path 103 from a maintenance board. When a CPU 3 or an I/O processor 4 is operated under said state, an address is set up in an instruction access address register 10 from a main storage access cntrol circuit 2. When the coincidence circuit 12 detects the coincidence of both the outputs 105, 106 of the registers 10, 11, a signal line 107 is made available, the coincidence is informed to a false fault generating circuit 13 and a false fault is generated. |
