| 摘要 |
PURPOSE:To simplify the constitution of the titled device and to improve the response speed by applying direct pulse width modulation to the difference of two numerical data represented normally in a binary code. CONSTITUTION:A numerical data content response signal generating circuit 2 generates respectively numerical data content response signals pa, pb to numerical data A and B inputted alternately in the period of 2<n>-bit so as to control an output level state holding circuit 3 comprising the sequence circuit. The signals pa, pb are bit signals generated when the bit width corresponding to each numerical data content in each 2<n>-bit period. Thus, a pulse width modulation signal of numerical data is outputted respectively from the circuit 3 at a time position counting the bit width corresponding to the content of the numerical data A(B) by the signal pa(pb), for example, by inverting the output level from the high (low) level to the low(high) level. Then a desired modulation output Y is obtained immediately from the circuit 3 by applying control in synchronizing with a data changeover clock CK4 whose level is inverted in the 2<n>-bit period. |
