发明名称 MULTI-STAGE ANALOG MULTIPLEX CIRCUIT
摘要 PURPOSE:To reduce the load for an IC power supply while reducing current consumption and to improve the transmission characteristic of an analog multiplexer by allowing an amplifier amplifying an input analog signal to be selected by a switch signal in a multi-stage analog multiplex circuit formed in an integrated circuit, interrupting a power current of an amplifier not selected and operating the selected amplifier only. CONSTITUTION:An input signal 65(SI) is a signal becoming an HIGH level for two periods' share of clocks. An output of a shift register is shifted sequentially at each clock according to a clock signal and outputs Q1, Q2, Q3, Q4 are as shown in Fig. Analog multiplexer switching signals by gates 67, 68, 69, 70 are as shown in SW1, SW2, SW3 and SW4. The SI and the SW1, the Q1 and the SW2, the Q2 and the SW3, and Q3 and the SW4 are respectively switching signals of the analog multiplexer and the amplifier at one-bit and the switching signal of the amplifier goes to an high level before one clock. A gate 79 is realized by eliminating the gate 67 by means of the method of change of the timing relation by one clock and shifting in order the sequence one by one.
申请公布号 JPS60239122(A) 申请公布日期 1985.11.28
申请号 JP19840095962 申请日期 1984.05.14
申请人 SUWA SEIKOSHA KK 发明人 YOKOYAMA TAKAO
分类号 H03F3/72;H03K5/15;H03K17/693 主分类号 H03F3/72
代理机构 代理人
主权项
地址