发明名称 PURGING SYSTEM OF TABLE BUFFER
摘要 PURPOSE:To perform rationally partial purging of TLB so as to improve speed characteristics, by performing the purging process when an object to be purged is accessed. CONSTITUTION:When one of numerous logic-real address pairs in a table buffer 10 is purged, the same address as the real address R of the address pair is set in a register 14 and the valid bit V of the register 14 is set to ''1''. Then the table buffer 10 is kept as it is without making any scanning operation on the buffer 10, even though the purge address PA is set in the register 14. The table buffer 10 is accessed whenever a logical address is set in an address register 12 and a relevant logical-real address pair is read out, and a comparator 18 compares the real address R of the read out logic-real address pair with the purge address PA of the register 14 and, when they do not coincide with each other, outputs an L-level output. When they coincide with each other, the comparator 18 outputs an H-level output.
申请公布号 JPS60238954(A) 申请公布日期 1985.11.27
申请号 JP19840094281 申请日期 1984.05.11
申请人 FUJITSU KK 发明人 SAITOU AKIYOSHI
分类号 G06F12/10;(IPC1-7):G06F12/10 主分类号 G06F12/10
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