Phase-locked loop with switchable phase detector.

摘要

The invention relates to a phase-locked loop with a phase detector and a clock pulse oscillator. The phase detector is in the form of a multiplying circuit for multiplying a received reference signal by a comparison signal. It is constituted by a plurality of signal channels 207(.) each receiving the reference signal and each comprising a cascade arrangement of a switching circuit 208(.) and a weighting network 209(.). This switching circuit is controlled by one or more sequences of main control pulses supplied by a pulse distributor circuit to which the clock pulses of the clock pulse oscillator are applied. The weighting network has a constant weighting factor which for the weighting network in the k<th> signal channel is equal to the signal sample n/< ANd >(to kTs) of a fundamental signal n/< ANd >(t) which is, for example, a pure sinusoidal signal and has a fundamental frequency fo. Herein to is a constant and Ts represents the reciprocal value of the clock pulse frequency fs of the clock pulse oscillator. For each sequence of main control pulses controlling the switching circuit 208(.) in the kth signal channel, this signal channel produces a main signal z(k, t). The main signals supplied by all the signal channels are added together in an adder arrangement 210.
<??>Since the weighting factors cannot be changed, the loop can only be locked onto one received frequency. So as to obtain a larger degree of flexibility and more specifically to enable locking of the loop also on frequencies which are an integral multiple p of the fundamental frequency, a clock pulse oscillator is chosen whose clock pulse frequency fs is an integral multiple N of the fundamental frequency. In addition, the pulse distributor circuit 204 has an input 206 for setting the parameter p and at least N distributor outputs to which the several clock pulses are applied. More specifically, the clock pulse having number n is applied to the distributor output having number np modulo N. The sequence of pulses thus occurring at these distributor outputs constitute the sequence of main control pulses already mentioned in the foregoing.