发明名称 DISPLAY CONTROLLER
摘要 PURPOSE:To reduce the scale of hardware so as to be integrated large scale in a display controller, by separating a process for processing the access time of a displaying picture data memory as a unit from another process for processing the time of dot clocks as a unit. CONSTITUTION:A frequency dividing circuit 7 gives a timing pulse necessary to the reading out time of a displaying picture data memory 2 to a counter by dividing a dot clock. Therefore, the counter 9 updates the content of the counter 9 by using the reading out time of the memory 2 as a unit. The data of the memory 2 read out to an output register 8 are selected in accordance with the content of the counter 9 and sent to another output register 3. The register 3 is shifted by the dot clock and its output is inputted in series in a shift register 4. Therefore, display can be started from an aimed optional bit position when an optional bit output of the register 4 is appropriately selected.
申请公布号 JPS60238928(A) 申请公布日期 1985.11.27
申请号 JP19840094584 申请日期 1984.05.14
申请人 MATSUSHITA DENKI SANGYO KK 发明人 DEGUCHI MASASHI;NISHIZAWA TEIJI;OZAWA SUMIO
分类号 G06F3/153;G06F3/14 主分类号 G06F3/153
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