| 摘要 |
PURPOSE:To reduce the load on a central processor and to transmit and receive data at a high speed by allowing a wiring logical device to take partial charge of control. CONSTITUTION:The data transmission/reception system consists of the 1st - the 4th address buses 102, 202, 302, and 402 for control, the 1st - the 4th data buses 101, 201, 301, and 401, a data transmitter receiver 1, a bus changeover switch 4, the central processor 2, and the wiring logical device 3. The wiring logical device 3 is equipped with a status information detecting circuit 31, control information generating circuit 32, data input circuit 33, data output circuit 34, control address generating circuit 35, interface circuit 36, and control circuit 37. The bus changeover switch 4 is switched to the side of the central processor 2 before data information is transferred from the data transmitter receiver 1 or to the data transmitter receiver 1, and the bus changeover switch 4 is switched to the side of the wiring logical device 3 during the transfer period. |
