Output interface for a three-state logic circuit in an integrated circuit using MOS transistors

摘要

An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.-floating) during any other logic state.