发明名称 PULSE GENERATING CIRCUIT
摘要 PURPOSE:To simplify the constitution of the circuit, determine the pulse width of an output pulse with one set value, and elimate the need to vary the set value by composing the pulse generating circuit of an UP/DOWN period counter and a comparator. CONSTITUTION:The pulse generating circuit consists of the UP/DOWN period counter 7 and comparator 8 and the period counter 7 is reset with an input pulse and starts counting up or down at a period nearly equal to the period of the input pulse. The output value of this period counter 7 is compared by the comparator 8 with the constant value to output an output pulse train. Then, the period counter 7 counts up in the former half of one period and counts down in the latter half of the period and the output (t) of the period counter 7 is compared with the preset threshold value t1 by the comparator 8; when t<=t1, a high level is outputted and when t>t1, a low level is outputted to hold the output pulse of the comparator 8 invariably in the center of the input pulse, determining the pulse width with one set value.
申请公布号 JPS60237715(A) 申请公布日期 1985.11.26
申请号 JP19840095091 申请日期 1984.05.11
申请人 MITSUBISHI DENKI KK 发明人 OGAWA JIYUNZOU
分类号 H03K5/05;H03K5/00;H03K5/135;H03K7/08;(IPC1-7):H03K5/135 主分类号 H03K5/05
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