发明名称 WIRE HARNESS TESTER
摘要 PURPOSE:To elevate the working efficiency with a reduced processing time by sending a signal to perform a reading of a memory circuit for setting the transfer of the normal connection mode synchronizing the changeover of switching circuits for checking with a counter circuit which steps by a clock signal. CONSTITUTION:A start signal P0 is applied to a startup signal input terminal 18 with a start key to open a gate circuit 17. A clock signal P1 is applied to a counter circuit 20 to advance it by one step with each clock signal. With each step, a reading address for reading a memory circuit 21 for setting the transfer of the normal connection mode is advanced by one at a time to read out the contents thereof while the switching circuits 15 for checking are changed over in response to a switching signal of the counter circuit 20. At each time of the operation, the output of the memory circuit and inputs from the switching circuits 15 for checking are applied to a comparison circuit 22 to collate.
申请公布号 JPS60237374(A) 申请公布日期 1985.11.26
申请号 JP19840094230 申请日期 1984.05.11
申请人 SHINDENGEN KOGYO KK;SUMITOMO DENSOU KK 发明人 SUZUKI TOSHIYUKI;GOTOU YASUBUMI;TAKASHIMA HIDEAKI;TANAKA TAKEHIKO;OKANO HIRONOBU;SASAKI KAZUO
分类号 G01R31/02 主分类号 G01R31/02
代理机构 代理人
主权项
地址