发明名称 Noise reduction by linear interpolation using a single sample-and-hold circuit
摘要 In a noise reduction circuit, a sample-and-hold circuit operating on a tracking mode is sampled in response to the occurrence of a noise impulse. The voltage sampled is stored in the capacitor of the sample-and-hold. A slope detector is responsive to the capacitor voltage for generating an output representative of the rate of variation of the capacitor voltage. A voltage-to-current converter is connected between the output of the slope detector and the capacitor for converting the voltage to a corresponding current and injecting the current to the capacitor when the rate of variation is positive and draining the current from the capacitor when the rate is negative.
申请公布号 US4555669(A) 申请公布日期 1985.11.26
申请号 US19840632875 申请日期 1984.07.20
申请人 VICTOR COMPANY OF JAPAN 发明人 NAMIKI, YASUOMI
分类号 H03G3/34;(IPC1-7):H03F1/26 主分类号 H03G3/34
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