| 摘要 |
The present invention consists of a multirate data receiver which will recover data at any of N data rates with no predetermined restrictions on the value of N. The data rate at which the receiver operates is selected by a single 1-of-N switch selection. An equalizer section is constructed for each of the N data rates but are all controlled by the same (common) automatic adjustment circuitry, which controls gain and frequency compensation. The output from one of the equalizer sections is selected by an analog multiplexer constructed of field effect transistor (FET) switch circuits. The recovered waveforms from the equalizer sections are processed by common circuitry to recover the transmitted data. Clock recovery may be accomplished, for example, by a digital phase locked loop constructed such that the characteristics of the loop filters and divide-by-M feedback counters are easily modified by logical signals controlled by the 1-of-N switches.
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