| 摘要 |
PURPOSE:To attain a sequential logic type digital phase comparator which has no malfunction due to noises, etc. by producing a compensation pulse in case the inside state of a sequential logic type phase comparator is changed to another state from a steady state and kept in that state for a period of time longer than the fixed threshold value. CONSTITUTION:A phase comparator main body 1 contains at its input side a circuit 3 which differentiates the input pulse signal, a circuit 5 which detects the phase threshold value and generates a correction pulse and a pair of gates 4 which add pulses given from both circuits 3 and 5. The circuit 5 applies a clock signal having a cycle equal to the time equivalent to the phase threshold value to an input terminal 501 and performs the clock differentiation at its inside. Then the circuit 5 produces a compensation pulse in case the negative pulse width of a signal U or D is larger than a clock cycle and then delivers an output signal V1 or R1. When a noise pulse N is applied to a signal V2, the output signal D is once set at ''0''. However the signal D is reset to ''1'' approximately after a differentiating clock cycle since the compensation pulse R1 is added to a signal R2.
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