| 摘要 |
PURPOSE:To attain a variable frame pulse system with which the probability is reduced for generation of wrong synchronization and the hardware scale is not increased so much, by using an artificial random pulse to a component bit of a frame pulse and changing said component bit over several frames. CONSTITUTION:For instance, a frame pulse is formed with three bits and an output pattern of an original polynomial (X<3>+X+1) is used. The clock pulses are impressed to each terminal (c) of flip-flop circuits D1-D3. These D1-D3 are all set at ''1'' in an initial mode, and the Q output is used as a frame pattern F1. When the next clock pulse is impressed, the D1 is set at ''0'' with D2 and D3 kept at ''1'' respectively. Then the Q output is used as the next frame pattern F2. In such a way, the Q outputs of D1-D3 produce successively frame patterns F1-F7 with impression of clock pulses. Furthermore the accuracy is increased compared with a fixed system which repeats 111 seven times, for example, since said series of frame patterns are equal to the artificial random pulse output. |
