HIGH-SPEED THREE-OPERAND N-BIT ADDER

摘要

An adder and a method for calculating a sum of three input operands. The adder comprises a pre-processor, a generator and a post-processor. The pre-processor creates an initial propagation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry in bit is propagated as a carry out bit as determined from a value of respective bit-positions of each of the three operands. The pre-processor creates an initial generation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry out bit is generated as determined from a value of respective bit-positions of each of the three operands. The generator generates a composite propagation vector and a composite generation vector from parallel prefix operations on the initial propagation vector and initial generation vector. The post-processor calculates the sum from the initial propagation vector, the composite propagation vector and the composite generation vector. The adder has a gate delay of 2log2(N)+4.