发明名称 GENERATING CIRCUIT OF PHASE LOCKED CLOCK
摘要 <p>PURPOSE:To offer a phase locked sampling pulse generating circuit with high accuracy capable of narrowing a blind sector width substantially through the addition of a small number of circuits by delaying the time of a sampling pulse, where a sample value for detecting a phase difference can be obtained, by micro time from the prescribed time. CONSTITUTION:A sampling signal generating circuit 10 is added to a conventional constitution. A pulse signal for sampling being an output of a VCO8, is delayed by micro time DELTAt1 in delay circuits 11 and 12, switched and selected by a switch 13, and made to a sampling pulse signal of an A/D converter 2. (c) in the figure shows that the switch 13 is switched with respect to an actual television signal, and is normally positioned at a terminal (b). However, it is switched to a terminal (a) or (c) for every half period of a chrominance subcarrier only for a burst period of each scanning line in order to compare phases, and the sampling is executed at the point where the + or -DELTAt1 is shifted with respect to the standard sampling timing. Thus the comparison with high accuracy can be possible.</p>
申请公布号 JPS60236596(A) 申请公布日期 1985.11.25
申请号 JP19850082352 申请日期 1985.04.19
申请人 HITACHI SEISAKUSHO KK 发明人 ACHIHA MASAHIKO
分类号 H04N11/04;H04N9/45 主分类号 H04N11/04
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