| 摘要 |
PURPOSE:To attain C-bit synchronization at each (n+1)-bit by converting an nB1C code signal into 1/m in parallel, and using a 2-bit data series suitable among parallel conversion outputs, thereby using a clock frequency-dividing the clock in synchronizing with the nB1C code data into 1/m. CONSTITUTION:A serial/parallel converter 10 (shift register) is operated with a clock in synchronizing with a frequency f0 of an nB1C code data inputted from an input terminal 6 and fetches the nB1C code data of consecutive m-bit. Then the serial/parallel converter 10 outputs the fetched m-bit data in parallel by using a signal subject to 1/m frequency division by a 1/m frequency divider from the clock of the frequency f0. A proper 2-bit output among 1/m parallel conversion outputs of the serial/parallel converter 10 is fed to a 2-input exclusive OR circuit 7. When the output signal of the frequency divider 11 is counted by (n+1)-time, the output is fed to an error detection circuit 8 together with output ''1'' from the exclusive OR circuit 7 and the state that the C-bit synchronizing condition is satisfied is outputted from the circuit 8. |
