发明名称 VOLTAGE CONVERTING AND HOLDING CIRCUIT
摘要 PURPOSE:To observe sequentially the change in an input signal by applying charging with other charging means in response to an input signal while a comparator compares a voltage held in one charging means with a sawtooth wave and executing alternately the operation. CONSTITUTION:An emitter current Ie of a transistor TRQ1 flows with a prescribed peak value in response to the input pulse. When a control circuit 9 turns on a TRQ2 and turns off Q3, Q4, Q5, the current Ie charges a capacitor 5. When a time t0 is elapsed after start of charging, the TRQ3 is turned on and the Q2, Q4 and Q5 are turned off. The capacitor 5 holds a voltage just before the TRQ2 is turned off and the current Ie charges a capacitor 6 (section t1). A comparator 10 compares a V5 with an output voltage V11 of a sawtooth wave generating circuit 11 during this time. After the section t1 is elapsed, the TRQ4 is turned on, the Q2, Q3, Q5 are turned off, a voltage V6 is held so as to discharge the capacitor 5. When the voltage V5 reaches zero, the capacitor 5 is charged (section t'2) while the voltage V6 is held by turning on and off the Q2 and Q3, Q4, Q5. The V6 and V11 are compared. The operation above is repeated afterward, the input signal is observed without intermission so as to obtain a voltage to be compared.
申请公布号 JPS60235520(A) 申请公布日期 1985.11.22
申请号 JP19840092120 申请日期 1984.05.08
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KANETAKE MASASHI;MICHIHASHI HIROYUKI
分类号 G05F1/56;H03K5/08;H03K5/24 主分类号 G05F1/56
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