| 摘要 |
PURPOSE:To eliminate the need for a circuit assuring the transmittability and to attain parallel transmission through lots of lines by providing a control signal line for synchronization in addition to an information transmission line. CONSTITUTION:A transmission line 130 is twisted pair multi-core cable and 11 kinds of communication lines are formed by 11 pairs of conductors. A line RM in the transmission line 4 is called a record mark and a signal line representing a section of a transmission frame in the transmission system. A line CLK is a clock line to synchronize a transmission timing and reception timing of the information. D7-D0 are information lines forming one byte information by 8 lines, the D7 is the MSB (most significant bit) and the D0 is the LSB (least significant bit). The transmission data stored in a buffer memory 104 is transmitted to a transmission register 107 and a signal is outputted to the information lines D0- D7 and a parity line Parity of the transmission line from a transmission driver 113 in synchronizing with the rise of the clock of the line CLK. |
