| 摘要 |
PURPOSE:To make the optimum design of a bit synchronising circuit, by detecting abnormal conditions such as omission of an input signal, etc., and out of bit synchronism and switching the answering frequency of the bit synchronizing circuit in accordance with the detected results. CONSTITUTION:A phase error is detected by reading a signal from a disk 1 by means of a reading means 3 and comparing the phases of the signal and a clock generated from a VCO10 at a phase comparator 8, and the detected phase difference is inputted in the VCO10 after it is integrated in an LPF9. The envelope of input signals is detected by an input signal detecting means 5 and, when an input signal is omitted, the answering frequency of the LPF9 is lowered. Moreover, the out of cycle of an input signal is detected by means of an out-of-synchronism detecting means 6 through a signal processing circuit 7 and when a detected outut exists, the answering frequency of the LPF9 is raised. Therefore, the optimum design of a bit synchronizing circuit can be realized. |
