| 摘要 |
An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus. At the beginning of the polling sequence, a bus base address register in each module is preset to a port 0 address by the CPU. A POLL signal is generated by the CPU and intercepted by the closest module, which responds by placing a module identification character on the data lines of the system bus. The CPU receives the module identification character, stores this character in a table and issues a bus base address for that module. Upon receipt of the bus base address, the module presently active in the polling sequence issues a POLL command to the next module on the system bus. The poll sequence is repeated until all modules have been assigned and have received a bus base address. |
