发明名称 CLOCK CONTROL CIRCUIT
摘要 PURPOSE:To prevent loss of information or the like due to troubles of a clock system by monitoring clocks supplied from an input/output device and switching them to internal clocks if supplied clocks are stopped. CONSTITUTION:A frequency dividing circuit 4 which devides the frequency of the first clock 1, a synchronizing circuit 5 which generates a synchronous output obtained by synchronizing a frequency division output 49 of the circuit 4 with another second clock inputted independently of the first clock 1, a pulse width threshold circuit 6 which outputs a clock stop signal when detecting that the pulse width of a synchronous output 59 outputted from the circuit 5 exceeds a prescribed value, and a clock switching circuit 7 which switches and outputs the first and the second clocks in accordance with a clock stop signal 69 outputted from the circuit 6 are provided. Consequently, the refresh operation of an external storage device is continued by the second clock 2 even if the first clock 1 supplied from the input/output device is stopped.
申请公布号 JPS60235223(A) 申请公布日期 1985.11.21
申请号 JP19840092055 申请日期 1984.05.09
申请人 NIPPON DENKI KK 发明人 MATSUMOTO HAJIME
分类号 G06F1/04 主分类号 G06F1/04
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