| 摘要 |
PURPOSE:To prevent increase in a pitch of mask layout and increase in a delay time by connecting an output signal line of a NAND circuit of an AND logic section to a gate of a P-channel MOSFET constituting a NAND circuit of an OR logic section directly. CONSTITUTION:The logical array consists of an AND logic section 1, an OR logic section 2, AND logic N-channel MOSFETQ11, Q12, Q13, Q14, OR logic P-channel MOSFETQ21, Q22, Q23, charging P-channel MOSFETQ31, Q32, Q33, Q34, discharging N-channel MOSFETQ41, Q42, Q43, Q44 and an inverter R2. The gate of the N-channel MOSFETQ41, Q42 and the P-channel MOSFETQ31, Q32 in the AND logic section 1 are connected to a clock signal phi1 and the gates of the N-channel MOSFETQ43, Q44 and the N-channel MOSFETQ33, Q34 in the OR logic section 2 are connected respectively to a clock signal phi2. |
