发明名称 CLOCK CONTROLLER
摘要 PURPOSE:To attain the effective debug, maintenance and diagnosis of an information processor by providing a function which stops quickly with the processor itself when a phenomenon is detected together with a function with which a system stops synchronously. CONSTITUTION:A phenomenon 45, i.e., the selection conditions of a phenomenon 43 is set to a mode register 44 of an information processor when it is desired that a clock is quickly stopped by an optional phenomenon 43 detected by the information processor itself as one of actions for clock control of a tight coupling information processing system. Then a mode register 49 is set so as to select an FF48. If the phenomenon 45 set at the register 44 is produced within a logical circuit 42 under such conditions, a phenomenon detection signal 47 is outputted from a selection circuit 46 to set the FF48. Then a clock stop signal 52 is outputted to a clock distribution circuit 40 from a selection circuit 51, and the clock of the information processor is stopped.
申请公布号 JPS60233739(A) 申请公布日期 1985.11.20
申请号 JP19840090393 申请日期 1984.05.07
申请人 NIPPON DENKI KK 发明人 MORIYAMA SHIYUUKICHI
分类号 G06F1/04;G06F11/07;G06F11/22 主分类号 G06F1/04
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