| 摘要 |
PURPOSE:To output surely a phase state independently of a pattern of a data signal by constituting a sequence circuit where a data signal is formed into a trigger signal making transition of comparison state and a timing signal is formed into an input signal via a delay circuit. CONSTITUTION:The timing signal is inputted respectively to inverters 3, 4, a delay circuit 5 and AND gates 6, 7, and an output of the inverters 3, 4 is inputted to AND gates 8, 9. A Q1 output of a D FF1 is inputted to the AND gate 8 via an OR circuit 10 and inputted also to the AND gate 7. An output of Q2 side of a D FF2 is inputted to the AND gate 18 via the OR circuit 10. The delay circuit 5 gives a delay of the inputted timing signal by a half of one bit time, its output is impressed to the AND gate 7 and then inputted to an inverter 11. An RZ or NRZ data signal is impressed to a T input of D FF1, 2 as a trigger signal.
|
