| 摘要 |
An improved latch capable of operation in an edge-triggered, data-handling mode and in an LSSD clocked mode. The latch generally comprises a polarity hold latch L1 connected to a polarity hold latch L2. The -C clock input of the latch is tied to the +B clock via an OR invert gate. Thus, during the loading of the L1 latch and data transferred to the L2 latch, the loading and transfer of false data is eliminated, while the latch otherwise conforms to LSSD rules and can be tested accordingly.
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