| 摘要 |
<p>A multi-processor system formed of a plurality of intelligent processing nodes interconnected by one or more transmission lines to form a shared resource cluster. The system is comprised of a multi-conductor bus including data and address lines. A plurality of units each has a random access memory connected to the bus in respective slots along the bus. The connection includes apparatus for slot identification for providing a respective coded signal combination representing a slot address to each unit as it is connected to the bus. Each unit has apparatus for storing its slot address, and register apparatus for storing a range of memory addresses assigned to that unit. Further apparatus in each unit accesses the random access memory of that unit on the basis of addresses received on the bus which fall within the range stored in the register apparatus.</p> |
