| 摘要 |
PURPOSE:To prevent the generation of a demodulation error at the increase of a transmission speed by testing the comparison between the preceding and succeeding signals of a receiving signal divided in each two bits at the rise and fall of a clock without using a delay circuit. CONSTITUTION:An receiving signal 11a is inputted to a receiving signal input terminal 11 of a demodulating circuit, a ''0'' signal 11a at each rise of a clock input 14a is detected by the 1st FF13, and at the detection, a Q' output 13a is turned to ''1'' only for the succeeding one period. The OR of the output 13a and the signal 11a is found out by an OR circuit 12 and its outputs 12a is applied to the data input of the 2nd FF15. A NOR output 16a corresponding to the clock input 14a is inputted from a NOR circuit 16 to the clock terminal of the FF15, the level of the output 12a of the circuit 12 is detected at the rise of the NOR output 16a and a Q output 15 from the FF15 is outputted to a demodulating signal output terminal 17 as a demodulated output. Thus, the generation of a demodulation error at the increase of the transmission speed is prevented without using a delay circuit. |
