| 摘要 |
PURPOSE:To detect an error also in incorrect transfer data by conneting plural inversion circuits for inverting parity bits outputted from plural transmission registers, decoding a selecting singnal and inhibiting the operation of the inversion circuit corresponding to the transmission register to be selected. CONSTITUTION:The transmission registers 11-14 store 8-bit data and 1-bit parity bits. The 8-bit data outputs from the registers 11-14 are inputted to a selecting circuit 2 and parity bit outputs are inputted to the circuit 2 through the inversion circuits 71-74. The circuit 2 inputs selecting signals 41, 42, selects the outputs of an optional transmission register and its corresponding inversion circuit in accordance with the selecting signals and supplies the selected outputs to a receiving register 3. On the other hand, a decoder 5 inputs selecting signals 41', 42', decodes these signals and turns signal lines 61-64 corresponding to the transmission register to be selected to the high level. Consequently, the inversion circuit connected to the transmission register to be selected is inhibited at its inverting operation. Thus, an error can be detected even if the inversion circuit executes malfunction. |
