| 摘要 |
<p>A data processor system includes a plurality of multiprocessor systems, and each multiprocessor system is connected through each memory control unit of each multiprocessor system. The multiprocessor system comprises a memory control unit, at least one central processing unit, at least one channel control unit, and at least one main memory unit. The central processing unit, channel control unit, and main memory unit are connected to the memory control unit via interface lines. The memory control unit (MCU0, MCU1) comprises at least two pipelines (PL1, PL11) and at least two access selecting circuits (S1, S2 ; S11, S12). One pipe-line (PL1) is used for access requests to the main memory unit belonging to the memory control unit, and the other pipe-line (PL11) is used for access requests to another main memory unit belonging to another memory control unit.</p> |
